LDPC decoders badly map on processor targets. We developped x86 decoder based on layer scheduling that take advantage of SIMD and multi-core features. Experimentations show that the proposed solution provide high throughputs and low latency compared to previous GPU and CPU works. Proposed solution fulfill SDR (Software Define Radio) requirements.
Textual message parsing is a complex task for embedded network device. Indeed, automaton used for this task badly map on embedded processor. To solve this issue a co-design based methodology was developped: automatic VHDL parser generation and software layer generation from BNF description.
Keyword(s) Co-design, parser, FSM, LEON-3.
Publication(s): IEEE ESL + under review (ACM TRETS).
Collaboration(s): D. Bromberg and L. Reveillere.
File(s): None yet.
Polar code is a new FEC family. It provides lower correction performances at same frame length than e.g. LDPC codes but they are easier to implement in Hw/Sw. We proposed efficient x86 and ARM implementations of Successive Cancellation decoders that reach up to Gbps on a single processor core.
Keyword(s) PolarCode, x86, SIMD (AVX2, NEON), MPMD (OpenMP).
Publication(s): IEEE TSP.
Collaboration(s): C. Leroux and C. Jego.
File(s): None yet.
To evaluate ealier the BER/FER performance of hardware LDPC decoders, fast simulation chains have to be developped. In this works we proposed world fastest LDPC GPU decoders. Implementations were based on horizontal layered algorihtm (MS, OMS, NMS, SPA), applied to floating and fixed point computations.
This work follows the previous one that target a reprogrammable architecture. Contrary to previous study, reconfigurable elements were removed to improve as possible the area and the power consumption of the generated ASIC/FPGA circuits. A FPGA-based demonstrator was developped to demonstrate the correctness of the works.Keyword(s) LDPC, FPGA, ASIC, ESL, unstructured, QC. Publication(s): IEEE TSP.
This template is an example of how easy it can be to create a landing page with just the Skeleton grid and a few custom styles. The entire demo is ~150 lines of CSS including comments (most of which is positioning the phones at the top).Keyword(s) LDPC, FPGA, ESL, graph, compiler, GPU.