Who am i ?

I received my M.Sc. degree in Electronics Engineering from the University of South Brittany, Lorient, France, in 2002 and my Ph.D degree in Information and Engineering Sciences and Technologies from the University of South Brittany in 2005. I was a Post-Doctoral fellow in 2005 to 2006 in CAIRN team at the INRIA/IRISA laboraroty from the University of Rennes 1, Lannion, France. Since September 2006, I hold an Assistant Professor position at the ENSEIRB-MATMECA engineering school from the Bordeaux Institute of Technlogy and the Laboratory of Integration from Materials to Systems (IMS) from the University of Bordeaux in Talence, France.
My current research interests include Algorithm-Architecture-Matching on both hardware (ASIC/FPGA) and software targets (CPU/DSP/GPGPU) and design methodlogies and ESL tools. During the latest years, i focused on the design of efficient ECC decoders for processor and GPU targets to meet flexibility and throughput performances required by Software Defined Radio applications.

Three main research topics

Processor and GPU programming. Parallel software optimization for SIMD, MIMD, SIMT targets for Software Defined Radio. Targets include x86 (AVX2, OpenMP), GPU (CUDA) and ARM (NEON) devices.
Design methodologies based on SystemC for system modeling and HLS. Tools (usage and internal algorithms) for hardware design speed-up such as HLS or co-design.
Design of RTL architectures for ASIC/FPGA targets. Includes dedicated digital design, co-design based ones and ASIP cores. Focuses on Error Correction Codes and Video processing applications.

Research activities (selected)

International journals
Book chapter
Conference articles (selected)

Reviewing activities

Student supervision

Current PhD Students
Former PhD-Students
Invited PhD-Students
Post-PdD Students
Research engineers
M.Sc. Graduates

Working hardware and software demonstrators

(Only works related to research articles are listed bellow)
GPP-based LDPC decoders (2015)

LDPC decoders badly map on processor targets. We developped x86 decoder based on layer scheduling that take advantage of SIMD and multi-core features. Experimentations show that the proposed solution provide high throughputs and low latency compared to previous GPU and CPU works. Proposed solution fulfill SDR (Software Define Radio) requirements.

Keyword(s) LDPC, x86, software, SIMD, MPMD.
Publication(s): IEEE TPDS, IEEE Com. letter.
Collaboration(s): C. Jego.
File(s): Git repository (x86), Git repository (ARM).

Co-design system for message parsing (2014-2008)

Textual message parsing is a complex task for embedded network device. Indeed, automaton used for this task badly map on embedded processor. To solve this issue a co-design based methodology was developped: automatic VHDL parser generation and software layer generation from BNF description.

Keyword(s) Co-design, parser, FSM, LEON-3.
Publication(s): IEEE ESL + under review (ACM TRETS).
Collaboration(s): D. Bromberg and L. Reveillere.
File(s): None yet.

GPP-based Polar code decoders (2014)

Polar code is a new FEC family. It provides lower correction performances at same frame length than e.g. LDPC codes but they are easier to implement in Hw/Sw. We proposed efficient x86 and ARM implementations of Successive Cancellation decoders that reach up to Gbps on a single processor core.

Keyword(s) PolarCode, x86, SIMD (AVX2, NEON), MPMD (OpenMP).
Publication(s): IEEE TSP.
Collaboration(s): C. Leroux and C. Jego.
File(s): None yet.

GPU-based LDPC decoders (2014)

To evaluate ealier the BER/FER performance of hardware LDPC decoders, fast simulation chains have to be developped. In this works we proposed world fastest LDPC GPU decoders. Implementations were based on horizontal layered algorihtm (MS, OMS, NMS, SPA), applied to floating and fixed point computations.

Keyword(s) LDPC, GPU, SIMD (Nvidia), SPMT (CUDA).
Publication(s): IEEE ESL.
Collaboration(s): C. Jego.
File(s): Git repository (float), Git repository (fixed).

Methodology for LDPC decoder generation (2013)

This work follows the previous one that target a reprogrammable architecture. Contrary to previous study, reconfigurable elements were removed to improve as possible the area and the power consumption of the generated ASIC/FPGA circuits. A FPGA-based demonstrator was developped to demonstrate the correctness of the works.

Keyword(s) LDPC, FPGA, ASIC, ESL, unstructured, QC. Publication(s): IEEE TSP.
Collaboration(s): C. Jego.
File(s): Not yet (On demand).
Reprogrammable LDPC decoder architecture (2012)

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Keyword(s) LDPC, FPGA, ESL, graph, compiler, GPU.
Publication(s): ACM TECS.
Collaboration(s): C. Jego.
File(s): Not yet (On demand).